1. Field of the Invention
The present invention relates in general to a method and an apparatus for reading/writing data from/into a semiconductor memory device, and more particularly to a method and an apparatus for reading/writing data from/into a semiconductor memory device, in which, instead of true and complementary data input/output lines connected respectively to true and complementary bit lines, true and complementary column decoding lines are used to perform data read/write operations, thereby reducing the area of a semiconductor memory chip.
2. Description of the Prior Art
Referring to FIG. 1, there is shown a circuit diagram of a conventional data read/write apparatus for a semiconductor memory device such as a dynamic random access memory (referred to hereinafter as DRAM) device. As shown in this drawing, the DRAM device comprises a plurality of memory cell array blocks 10, each of which includes a plurality of memory cells 11 for storing data therein. Although not shown, each of the memory cells 11 is provided with one NMOS transistor and one capacitor.
The conventional data read/write apparatus comprises a plurality of bit line sense amplifier array blocks 12, each of which includes a plurality of bit line sense amplifiers 13 for sense-amplifying the data which are transferred from the memory cells 11 to true and complementary bit lines BL and /BL.
The conventional data read/write apparatus further comprises transfer transistors Q1 and Q3 for transferring the data on the bit lines BL to a true data input/output line IO in response to an output signal Yi from a column decoder (not shown), transfer transistors Q2 and Q4 for transferring the data on the bit lines BL to a complementary data input/output line/IO in response to the output signal Yi from the column decoder, a read sense amplifier 15 for sense-amplifying the data on the data input/output lines IO and /IO and transferring the sense-amplified data to a data output buffer (not shown), and a write driver 14 for transferring external write data to the data input/output lines IO and /IO.
Although not shown, a precharge circuit is provided to maintain the true and complementary bit lines BL and /BL at a precharge voltage level Vblp in a standby mode.
The operation of the conventional data read/write apparatus for the DRAM device with the above-mentioned construction will hereinafter be described.
First, when a signal/RAS which is a main signal for operating the DRAM device is made active, address signals from an address buffer (not shown) are received. At this time, a row decoding operation is performed which decodes the received address signals and selects one of word lines to the memory cell array block 10 in accordance with the decoded result. Data from the memory cells 11 connected to the selected word line are placed on the bit lines BL and /BL. At this time, the data placed on the bit lines BL and /BL have a feeble signal level. For this reason, the bin line sense amplifiers 13 are driven to sense-amplify the data on the bit lines BL and /BL to a supply voltage level Vcc and a ground voltage level vss. The transfer transistors Q1-Q4 act to transfer the data on the bit lines BL and /BL, sense-amplified by the bit line sense amplifiers 13, respectively to the data input/output lines IO and /IO in response to the output signal Yi from the column decoder. In more detail, the transfer transistors Q1-Q4 select one of columns in response to the output signal Yi from the column decoder. The data on the bit lines BL and /BL of the selected column are placed respectively on the data input/output lines IO and /IO by the turned-on transfer transistors Q1 and Q2 or Q3 and Q4. Then, the read sense amplifier 15 sense-amplifies the data on the data input/output lines IO and /IO and transfers the sense-amplified data to the data output buffer. On the other hand, external write data are placed on the data input/output lines IO and /IO by the write driver 14. The write data placed on the data input/output lines IO and /IO are written into the memory cell 11 by the bit line sense amplifier 13 of a column selected by the output signal Yi from the column decoder.
Referring to FIG. 2, there is shown a circuit diagram of another conventional data read/write apparatus for a semiconductor memory device. Some parts in this drawing are the same as those in FIG. 1. Therefore, like reference numerals designate like parts. As shown in this drawing, the true and complementary bit lines BL and /BL are connected to a plurality of true and complementary input/output lines IO0 and /IO0 and IO1 and /IO1 to embody a wide bit memory capacity.
In FIG. 2, a plurality of columns are simultaneously selected by one column address. In order to simultaneously read a plurality of data from the memory cells 11 in the selected columns, the same number of true and complementary input/output lines as the selected columns are required. For this reason, many true and complementary input/output lines to each bit line sense amplifier are required in wide bit memory devices with a large number of input/output bits. This results in an increase in the area of a semiconductor memory chip.